學系成員

1. Shu-Yen Lin, Chun-Hsiang Huang, Chih-hao Chao, Keng-Hsien Huang, and An-Yeu Wu, “Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks,” in IEEE Trans. Computers, vol. 52, pp. 1156–1168, Sept. 2008. (SCI, EI)
2. Shu-Yen Lin, Wen-Chung Shen, Chan-Cheng Hsu, and An-Yeu Wu, “Fault-tolerant Router with Built-in Self-test/Self-diagnosis and Fault-isolation Circuits for 2D-mesh Based Chip Multiprocessor," International Journal of Electrical Engineering (IJEE), vol. 16, no. 3, pp. 213-222, June 2009 (EI)
3. Kun-Chih Chen, Shu-Yen Lin, Wen-Chung Shen, and An-Yeu Wu, “A scalable built-in self-recovery (BISR) VLSI architecture and design methodology for 2D-mesh based on-chip networks, ” in Design Automation for Embedded Systems, vol.15, no.2, pp. 111-132, April 2011. (SCI, EI)
4. Kun-Chih Chen, Shu-Yen Lin, Hui-Shun Hung, and An-Yeu (Andy) Wu, “Topology-Aware Adaptive Routing for Non-Stationary Irregular Mesh in Throttled 3D NoC Systems,” in IEEE Trans. Parallel and Distributed Systems, vol.24, no.10, pp. 2109-2120, Oct. 2013. (SCI, EI)
5. Chih-Hao Chao, Kun-Chih Chen, Tsu-Chu Yin, Shu-Yen Lin and An-Yeu (Andy) Wu, “Transport Layer Assisted Routing for Run-Time Thermal Management of 3D NoC Systems,” in ACM Trans. Embedded Computing Systems, vol.13, no.1, article 11, Aug. 2013. (SCI, EI)
6. En-Jui Chang, Hsien-Kai Hsin, Shu-Yen Lin, and An-Yeu (Andy) Wu, “Path-Congestion-Aware Adaptive Routing with a Contention Prediction Scheme for Network-on-Chip Systems,” in IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, issue 1, pp. 113-126, Jan. 2014. (SCI, EI)
7. En-Jui Chang, Hsien-Kai Hsin, Chih-Hao Chao, Shu-Yen Lin, and An-Yeu (Andy) Wu, “Regional ACO-Based Cascaded Adaptive Routing for Load Balancing in Mesh-Based Network-on-Chip Systems,” accepted for publication in IEEE Trans. Computers, 2014. (SCI, EI)
8. Hsiu-Chuan Shih, Pei-Wen Luo, Jen-Chieh Yeh, Shu-Yen Lin, Ding-Ming Kwai, Shih-Lien Lu, Andre Schaefer, and Cheng-Wen Wu, “DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool,” in IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 33, no. 9, pp. 1356 – 1369, 2014. (SCI, EI)
9. Yu-Fu Yeh, Shu-Yen Lin, and Chung-Yang (Ric) Huang, “Fast and Accurate MPSoC Virtual Platform Simulation with Parallel Out-of-Order Execution Approach,” Journal of the Chinese Institute of Engineers (JCIE). (Accepted) (SCI, EI)

1. Ting-Jung Lin, Shu-Yen Lin and An-Yeu Wu, “Traffic-Balanced IP Mapping Algorithm for 2D-mesh On-Chip-Networks," in Proc. IEEE Workshop on Signal Processing Systems (SiPS-2008), DC, USA, pp. 200-203, Oct. 2008.

2. Shu-Yen Lin, Wen-Chung Shen, Chan-Cheng Hsu, Chih-Hao Chao, and An-Yeu (Andy) Wu, “Fault-tolerant Router with Built-in Self-test/Self-diagnosis and Fault-isolation Circuits for 2D-mesh Based Chip Multiprocessor Systems,” in Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2009), Hsinchu, TAIWAN, April 2009.

3. Shu-Yen Lin, Chan-cheng Hsu, and An-Yeu (Andy) Wu, “A Scalable Built-in Self-Test/Self-Diagnosis Architecture for 2D-mesh Based Chip Multiprocessor Systems,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS-2009), pp. 2317-2320, Taipei, TAIWAN, May 2009.

4. Shu-Yen Lin, Tzu-Chu Yin, Hao-Yu Wang, and An-Yeu Wu “Traffic-and Thermal-Aware Routing for Throttled Three-Dimensional Network-on-Chip Systems,” in Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2011), Hsinchu, TAIWAN, April 2011.

5. Chih-Hao Chao, Tzu-Chu Yin, Shu-Yen Lin, An-Yeu Wu “Transport Layer Assisted Routing for Non-Stationary Irregular Mesh of Thermal-Aware 3D Network-on-Chip Systems ,” in 24th IEEE International SOC Conference (SOCC-2011), pp. 284-289, Sep. 2011.

6. Tzu-Chu Yin, Chih-Hao Chao, Shu-Yen Lin, and An-Yeu (Andy) Wu, “Design of Transport Layer Assisted Routing for Thermal-Aware 3D Network-on-Chip,” in Asia Pacific Signal and Information Processing Association(APSIPA), Dec., 2011.

7. Kun-Chih Chen, Chih-Hao Chao, Shu-Yen Lin, Hui-Shun Hung, and An-Yeu Andy Wu, “Transport-Layer Assisted Vertical Traffic Balanced Routing for Thermal-Aware Three-Dimensional Network-on-Chip Systems,” in Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2012), Hsinchu, TAIWAN, April 2012.

8. Kun-Chih Chen, Shu-Yen Lin, Hui-Shun Hung and An-Yeu Wu, “Traffic-Balanced Topology-Aware Multiple Routing Adjustment for Throttled 3D NoC Systems,” in IEEE Workshop on Signal Processing Systems (SIPS 2012), October 2012.

9. Kun-Chih Chen, Shu-Yen Lin, and An-Yeu (Andy) Wu, “Design of Thermal Management Unit with Vertical Throttling Scheme for Proactive Thermal-aware 3D NoC Systems,” in IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT-2013), pp.118-121, Hsinchu, Taiwan, April 2013.

10. Shu-Yen Lin, Cheng-Hung Lin, and Ho-Yun Su, “Thermal-Aware Task Mapping for Reconfigurable Channel Decoding," in International Symposium on Bioelectronics and Bioinformatics (ISBB), 2014.
11. Shu-Yen Lin and Jin-Yi Lin, “Thermal-Aware Architecture and Mapping for Multi-Channel Three-Dimensional DRAM Systems,” in Global Conference on Consumer Electronics (GCCE), pp.713-714, Tokyo, Japan, October 2014.
12. Shu-Yen Lin, Cheng-Hung Lin, and Ho-Yun Su, “Thermal-Aware Kernel Mapping for Three-Dimensional Multi-Mode Channel Decoding,” in Global Conference on Consumer Electronics (GCCE), pp.630-631, Tokyo, Japan, October 2014.
13. Shu-Yen Lin, Cheng-Hung Lin, and Ho-Yun Su, “’Block-based SRAM Architecture and Thermal-Aware Memory Mappings for Three-dimensional Channel Decoding Systems,” IEEE 4th Global Conference on Consumer Electronics (GCCE), pp. 277-278, Osaka, Japan, October 2015.
14. (2nd price of best paper award) Shu-Yen Lin, Jin-Yi Lin, Kai-Wei Chang, and Cheng-Hung Huang, “Real-Time Data Compression for Thermal-controlled Three-Dimensional DRAM Systems,” IEEE 4th Global Conference on Consumer Electronics (GCCE), pp. 48 – 49, Osaka, Japan, 2015.
15. Shu-Yen Lin Ya-chun Chang, Ming-Rong Song, Chong-Siao Ye, Jin-Yi Lin, and Cheng-Hung Lin, “Context-predicted Power-managed Selection for the Location System of the Android Smart Devices,” Symposium on Engineering, Medicine and Biology Applications (SEMBA), 2016.
16. Shu-Yen Lin, Jin-Yi Lin, and Cheng-Hung Lin, “A Reconfigurable Near-Data Systolic Array Accelerator for the Three-Dimensional DRAM Systems,” IEEE 5th Global Conference on Consumer Electronics (GCCE), Kyoto, Japan, 2016. (Accepted) (Candidate of best paper award)

1. (主持人) 適用於三維動態記憶體系統之溫度-功耗-效能共同設計(I), 102-2218-E-155-005-, 科技部, 2013/08/01 至 2014/07/31.
2. (主持人) 無線超高畫質電源管控三維晶片系統之溫度控制器關鍵矽智產設計(I), 103-2221-E-155-077-, 科技部, 2014/08/01 至 2015/07/31.
3. (主持人) 次世代三維記憶體處理器系統之演算法與架構設計, 104-2221-E-155 -044 -, 科技部, 2015/08/01 至 2016/10/31.
4. (主持人) 三維混合記憶體系統之高可靠/低功耗/抗高溫存取控制器設計, 105-2221-E-155-076 -, 科技部, 2016/08/01 至 2017/7/31.

1. Shu-Yen Lin, An-Yeu Wu, “Chapter 4: Routing Algorithms for Irregular Mesh-based Network-on-Chip,” in Multi-core Embedded System (Georgios Kornaros eds.), pp. 111-154, CRC Press, April 2010.

2. Kun-Chih Chen, Chi-Hao Chao, Shu-Yen Lin, and An-Yeu (Andy) Wu, “Chapter 12: Thermal- and Traffic-Aware Routing for 3D NoC Systems,” in Routing Algorithms in Networks-on-Chip (M. Palesi and M. Daneshtalab eds.), Springer, to appear in Nov. 2013.

1. 2008 VLSI/CAD最佳論文獎入圍 (Candidacy of Best Paper Award for VLSI/CAD 2008)
2. 2011 VLSI/CAD最佳論文獎 (Best Paper Award for VLSI/CAD 2011)
3. IEEE GCCE傑出論文獎（2nd Price of GCCE 2015 Excellent Paper Award，2015/10/29）。
獲獎論文名稱：Real-Time Data Compression for Thermal-controlled Three-Dimensional DRAM Systems
4. 2016年第十二屆 全國電子設計創意競賽佳作獎
競賽題目：用於次世代記憶體處理器系統之乘加器架構設計(林晉毅、林浩德)
5. 2016第十六屆旺宏金矽獎優勝獎
競賽題目：適用於多模式三維晶片解碼系統之溫度與效能感知映射演算法與架構設計 (林浩德、蘇河雲)